View TMP91PW11F_367807.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91PW11
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (NMI , INT0, INTRTC), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP91PW11
Low Voltage/Low Power CMOS 16-bit Microcontroller
TMP91PW11F 1. Outline and Device Characteristics
The TMP91PW11 is OTP type MCU which includes 128 Kbyte One-time PROM. Using the adapter-socket, you can write and verify the data for the TMP91CW11 by general EPROM programmer. The TMP91PW11 has the same pin-assignment as the TMP91CW11 (Mask ROM type). Writing the program to Built-in PROM, the TMP91PW11 operates as the same way as the TMP91CW11.
MCU
TMP91PW11F
ROM
OTP 128 Kbyte
RAM
4 Kbyte
Package
P-LQFP100-1414-0.50C
Adapter Socket
BM11129
000707EBP1
For ADiscussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be mADe at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trADe laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
91PW11-1
2003-03-31
TMP91PW11
ADTRG AN0 to AN7 (P50 to P57) AVCC AVSS VREFL VREFH SO0 (P93) SI0 (P94) SCK0 (P95) SO1 (P42) SI1 (P41) SCK1 (P40) TXD2 (P60) RXD2 (P61) SCK2 (P62) TXD3 (P63) RXD3 (P64) SCK3 (P65)
CPU (TLCS-900L1) 10-Bit 8ch AD Converter XWA XBC XDE XHL XIX XIY XIZ XSP W B D H IX IY IZ SP 32 bits Serial I/ O (CH.1) SR PC F A C E L
VCC [3] VSS [3] OSC1 Clock Gear OSC2 XT1 (P96) XT2 (P97) CLK ALE EA AM8/16 RESET RD (P30) WR (P31) HWR (P32) WAIT (P33) BUSRQ (P34) BUSAK (P35) R/W (P36) P37 X1 X2
Serial I/ O (CH.0)
Serial I/O (CH. 2) Port 3 Serial I/O (CH. 3) 4-KB RAM
TXD4 (P66) RXD4 (P67)
SERIAL I/O (CH. 4)
Port 0 Port 1 Port 2
AD0 to AD7 (P00 to P07) AD8/A8 to AD15/A15 (P10 to P17) A0/A16 to A7/A23 (P20 to P27)
SDA/SO5 (P90) SCL/SI5 (91) SCK5 (P92) TI0 (P70)
Serial Bus Interface Controller
8-Bit Timer (Timer 0) 8-Bit Timer (Timer 1) Port A PA0 to PA6 SCOUT (PA7)
TO1 (P71)
TO2(P72)
8-Bit Timer (Timer 2) 8-Bit Timer (Timer 3)
128-KB PROM Watchdog Timer
TO3 (P73))
WDTOUT
INT4/TI4 (P80) INT5/TI5 (P81) TO4 (P82) TO5 (P83) INT6/TI6 (P84) INT7/TI7 (P85) TO6 (P86)
16-Bit Timer (Timer 4) 16-Bit Timer (Timer 5) Real Time Counter
Interrupt Controller
NMI INT0 (P87)
CS/WAIT Controller (3-Block)
CS0 (P40) CS1 (P41) CS2 (P42)
Figure 1.1 TMP91PW11 block diagram
91PW11-2
2003-03-31
TMP91PW11
2.
Pin Assignment and Pin Functions
The assignment of input/output pins for the TMP91PW11F, their names and outline functions are described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of TMP91PW11F.
Programmable Pull Up Pull Down
Pin No.
Programmable
TMP91PW11
TMP91PW11
P66/TXD4 P67/RXD4 VSS P50/AN0 P51/AN1 P52/AN2
Pin No.
Pull Down
Pull Up
88 P65/CTS3/SLCK3 87 P64/RXD3 86 P63/TXD3 85 P62/CTS2/SLCK2 84 P61/RXD2 83 P60/TXD2 82 P42/CS2/SO1 81 P41/CS1/SI1 80 P40/CS0/SCK1 79 P37 78 P36/R/W 77 P35/BUSAK 76 P34/BUSRQ 75 P33/WAIT 74 P32/HWR 73 P31/WR 72 P30/RD 71 P27/A7/A23 70 P26/A6/A22 69 P25/A5/A21 68 P24/A4/A20 67 P23/A3/A19 66 P22/A2/A18 65 P21/A1/A17
89 90 91 92 93 94
SIO
P53/AN3/ADTRG 95 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC NMI P70/TI0 P71/TO1 P72/TO2 P73/TO3 P80/INT4/TI4 96 97 98 99
100
ADC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Timer
P81/INT5/TI5 P82/TO4 P83/TO5 P84/INT6/TI6 P85/INT7/TI7 P86/TO6 P87/INT0 P90/SDA/SO5 P91/SCL/SI5 P92/SCK5 P93/SO0 P94/SI0 P95/SCK0 AM8/16 CLK VCC VSS X1
top view LQFP100
64 P20/A0/A16 63 VCC 62 VSS 61 WDTOUT 60 P17/AD15/A15 59 P16/AD14/A14 58 P15/AD13/A13 57 P14/AD12/A12 56 P13/AD11/A11 55 P12/AD10/A10 54 P11/AD9/A9 53 P10/AD8/A8 52 P07/AD7 51 P06/AD6 50 P05/AD5 49 P04/AD4 48 P03/AD3 47 P02/AD2 46 P01/AD1 45 P00/AD0 44 VCC 43 ALE 42 PA7/SCOUT 41 PA6 40 PA5 39 PA4 38 PA3
SIO
Clock mode
X2 EA RESET P96/XT1 P97/XT2 TEST1 TEST2 PA0 PA1 PA2
Figure 2.1.1 Pin assignment
91PW11-3
2003-03-31
Memory Interface
TMP91PW11
2.2
Pin Names and Functions
The names of input/output pins and their functions are described below.
Table 2.2.1 Pin names and functions (1/4) Pin name
P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30
RD
Number of pins
8 8
I/O
Function
I/O Port 0: I/O port that allows selection of I/O on a bit basis Tri-state Address/data (lower): Bits 0 to 7 of address/data bus I/O Port 1: I/O port that allows selection of I/O on a bit basis Tri-state Address data (upper): Bits 8 to 15 of address/data bus Output Address: 8 to 15 of address bus I/O Port 2: I/O port that allows selection of I/O on a bit basis (with pull-up resistor) Output Address: Bits 0 to 7 of address bus Output Address: Bits 16 to 23 of address bus Output Port 30: Output port Output Read: Strobe signal for reading external memory Output Port 31: Output port Output Write: Strobe signal for writing data on pins AD0 to 7 I/O Port 32: I/O port (with pull-up resistor) Output High write: Strobe signal for writing data on pins AD8 to 15 I/O Port 33: I/O port (with pull-up resistor) Input Wait: Pin used to request CPU bus wait I/O Port34: I/O port(with pull-up resistor) Input Bus request: Signal used to request high impedance for AD0 to 15, A0-23, RD , WR , HWR , R/ W , RAS , CS0 , CS1 , and CS2 pins. (For external DMAC) I/O Port 35: I/O port (with pull-up resistor) Output Bus acknowledge: Signal indicating that AD0 to 15, A0 to 23, R RD , WR , HWR , R/ W , RAS , CS0 , CS1 , and CS2 pins are at high impedance after receiving BUSRQ. (For external DMAC) I/O Port 36: I/O port (with pull-up resistor) Output Read/write: 1 represents read or dummy cycle; 0, write cycle. I/O Port 37: I/O port (with pull-up resistor) I/O Port 40: I/O port (with pull-up resistor) Output Chip select 0: Outputs 0 when address is within specified address area. I/O Serial clock I/O 1
8
1 1 1 1 1
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
1
P36 R/ W P37 P40
CS0
1 1 1
SCK1
Note: This device's built-in memory or built-in I/O cannot be accessed with the external DMA controller, using the BUSRQ and BUSAK signals.
91PW11-4
2003-03-31
TMP91PW11
Table 2.2.2 Pin names and functions (2/4) Pin name
P41
CS1
Number of pins
1
I/O
Function
I/O Port 41: I/O port (with pull-up resistor) Output Chip select 1: Outputs 0 if address is within specified address area. Input Serial receive data 1 I/O Port 42: I/O port (with pull-down resistor) Output Chip select 2: Outputs 0 if address is within specified address area. Output Serial send data 1 Input Port5: Input port Input Analog input: Analog signal input for AD converter Input Port 53: Input Port Input Analog input Analog signal input for AD converter Input AD external trigger Input Port 5: Input Port Input Analog input: Analog signal input for AD converter Input Pin for high level reference voltage input to AD converter Input Pin for low level reference voltage input to AD converter I/O Port 60: I/O port (Programmable open drain) Output Serial send data 2 I/O Port 61: I/O port Input Serial receive data 2 I/O Port 62: I/O port Input serial data send enable 2 (Clear To Send) I/O Serial Clock I/O 2 I/O Port 63: I/O port Output Serial send data 3 I/O Port 64: I/O port Input Serial receive data 3 I/O Port 65: I/O port Input Serial data send enable 3 (Clear To Send) I/O Serial Clock I/O 3 I/O Port 66: I/O port Output Serial send data 4 I/O Port 67: I/O port Input Serial receive data 4 I/O Port 70: I/O port Input Timer input 0: timer 0 input I/O Port 71: I/O port Output Timer output 1: Timer 0 or 1 output I/O Port 72: I/O port Output PWM output 2: 8-bit PWM timer 2 output I/O Port 73: I/O port Output PWM output 3: 8-bit PWM timer 3 output
SI1 P42
CS2
1
SO1 P50 to P52 AN0 to AN7 P53 AN3
ADTRG
3 1
P54 to P57 AN4 to AN7 VREFH VREFL P60 TXD2 P61 RXD2 P62
CTS2
4 1 1 1 1 1
SCLK2 P63 TXD3 P64 RXD3 P65
CTS3
1 1 1
SCLK3 P66 TXD4 P67 RXD4 P70 TI0 P71 TO1 P72 TO2 P73 TO3 1 1 1 1 1 1
91PW11-5
2003-03-31
TMP91PW11
Table 2.2.3 Pin names and functions (3/4) Pin name
P80 TI4 INT4 P81 TI5 INT5 P82 TO4 P83 TO5 P84 TI6 INT6 P85 TI7 INT7 P86 TO6 P87 INT0 P90 SDA SO5 P91 SCL SI5 P92 SCK5 P93 SO0 P94 SI0 P95 SCK0 PA0 to PA5 PA6
Number of pins
1
I/O
Function
I/O Port 80: I/O port Input Timer input 4: Timer 4 count/capture trigger signal input Input Interrupt request pin 4: Interrupt request pin with programmable rising/ falling edge I/O Port 81: I/O port Input Timer input 5: Timer 4 count/capture trigger signal input Input Interrupt request pin 5: Interrupt request pin with rising edge I/O Port 82: I/O port Output Timer output 4: Timer 4 output pin I/O Port 83: I/O port Output Timer output 5: Timer 4 output pin I/O Port 84: I/O port Input Timer input 6: Timer 5 count/capture trigger signal input Input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge I/O Port 85: I/O port Input Timer input 7: Timer 5 count/capture trigger signal input Input Interrupt request pin 7: Interrupt request pin with rising edge I/O Port 86: I/O port Output Timer output 6: Timer 5 output pin I/O Port 87: I/O port Input Interrupt request pin 0: Interrupt request pin with programmable level/rising edge I/O Port 90: I/O port (Programmable open-drain) I/O SBI I2C bus mode channel data Output Serial send data 5 I/O Port 91: I/O port (Programmable open drain) I/O SBI I2C bus mode clock Input Serial receive data 5 I/O Port 92: I/O port I/O Serial Clock I/O 5 I/O Port 93: I/O port (Programmable open drain) Output Serial send data 0 I/O Port 94: I/O port Input Serial receive data 0 I/O Port 95: I/O port I/O Serial clock I/O 0 I/O Port A0 to A5: I/O ports (large current output) I/O Port A6: I/O port
1
1 1 1
1
1 1
1
1
1 1 1 1 6 1
91PW11-6
2003-03-31
TMP91PW11
Table 2.2.4 Pin names and functions (4/4) Pin name
PA7 SCOUT
WDTOUT NMI
Number of pins
1
I/O
Function
I/O Port A7: I/O port Output System Clock Output: Outputs system clock or 2 times oscillation clock for synchronizing to external circuit. Output Watchdog timer output pin Input Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at rising edge by program. Output Clock output: Outputs [System Clock 2] Clock. Pulled-up during reset. can be disabled for reducing noise. Input Fixed to 1. Input Fixed to 1. Output Address Latch Enable (Can be disabled for reducing noise.) Input Reset: Initializes LSI. (With pull-up resistor) I/O High Frequency Oscillator connecting pin Input Low Frequency Oscillator connecting pin I/O Port 96: I/O port (Open Drain Output) Output Low Frequency Oscillator connecting pin I/O Port 97: I/O port (Open Drain Output) Output TEST1 Should be connected with TEST2 pin. /Input Power supply pin (All VCC pins are connected to the power supply source.) GND pin (All Vss pins are connected to the GND (0 V).) Power supply pin for AD converter GND pin for AD converter (0 V)
1 1 1
CLK
EA
1 1 1 1 2 1 1 2 3 3 1 1
AM8/ 16 ALE
RESET
X1/X2 XT1 P96 XT2 P97 TEST1/TEST2 VCC VSS AVCC AVSS
Note: Built-in pull-up/pull-down resistors can be released from the pins other than the RESET pin by software.
91PW11-7
2003-03-31
TMP91PW11
2.3
PROM mode
Table 2.3.1 Name and function of PROM mode
Pin function
A7 to A0 A15 to A8 A16 D7 to D0
CE OE PGM
Number of pins
8 8 1 8 1 1 1 1 4 4
Input / Output
Input
Function
Pin name (MCU mode)
P27 to P20 P17 to P10 P33 P07 to P00 P32 P30 P31
EA
Input Memory address of program Input I/O Memory data of program Input Chip enable Input Output enable Input Program control Power supply 12.75 V/5 V (Power supply of program) Power supply 6.25 V/5 V Power supply 0 V
VPP VCC VSS
VCC, AVCC VSS, AVSS
Pin function
P34
RESET
Number of pins
1 1 1 1 1 1 7
Input/ Output
Input Fix to low level (security pin) Input Input Output Open Input Output Self oscillation with resonator Fix to low level (PROM mode)
Pin state
CLK ALE X1 X2 P42 to P40 P37 to P35 AM8/ 16 TEST1/TEST2 P57 to P50 P67 to P60 P73 to P70 P87 to P80 P97 to P90 PA7 to PA0 VREFH VREFL
NMI WDTOUT
Input Fix to high level Input / Short Output
2
48
I/O Open
91PW11-8
2003-03-31
TMP91PW11
3.
Operation
This section describes the functions and basic operational blocks of the TMP91PW11. The TMP91PW11 has PROM in place of the mask ROM which is included in the TMP91CW11. The other configuration and functions are the same as the TMP91CW11. Regarding the function of the TMP91PW11, which is not described herein, see the TMP91CW11. The TMP91PW11 has two operational modes: MCU mode and PROM mode.
3.1 MCU mode
(1) Mode-setting and function The MCU mode is set by releasing the CLK pin (Pin open). operation is the same as TMP91CW11. (2) Memory-map The memory map of TMP91PW11 is the same as that of TMP91CW11. The memory map in MCU mode and the memory map in PROM mode are shown in Figure 3.2.1. In the MCU mode, the
91PW11-9
2003-03-31
TMP91PW11
3.2 Memory Map
Figure 3.2.1 are the memory map of the TMP91PW11.
000000H Internal I/O 000080H Internal RAM 001080H
0000H
External Area
Internal PROM (128 Kbytes)
FE0000H Internal PROM (128 Kbytes) FFFFFFH In MCU mode
1FFFFH
In PROM mode
Figure 3.2.1 Memory map
91PW11-10
2003-03-31
TMP91PW11
4.
4.1
Electrical Characteristics
Absolute Maximum Ratings
X used in an expression shows a frequency of clock fFPH selected by SYSCR1 . If a clock gear or a low speed oscillator is selected, a value of X is different. The value as an example is calculated at fc, gear 1/fc (SYSCR1 0000). Parameter
Power Supply voltage Program voltage Input Voltage Output Voltage Output Current (per pin)
Symbol
VCC UPP VIN VOUT IOUT1 IOUT2 IOUT3
EA
Pin
Rating
0.5 to 6.5 0.5 to 13.0 0.5 to VCC 0.5 0.5 0.5 to VCC 20 2 2 120 80 80 600 260 65 to 150 40 to 85
Unit
V V V V mA mA mA mA mA mA mW C C C
P96, P97, PA0 to A5, P60, P91 to 93 (for open-drain) only PA0 to A5 except PA0 to A5 Total PA0 to A5 Total
Output Current (total)
IOUT1 IOUT2 IOUT3
Power Dissipation (Ta Soldering Temperature Storage Temperature Operating Temperature
85C)
PD Tsolder TSTG Topr
Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
91PW11-15
2003-03-31
TMP91PW11
4.2
DC Characteristics (1/2) (Vss
Parameter Symbol
0 V, Ta
40 to 85C)
Min
4.5
Condition
fc 4 to 25 MHz fc 4 to 12.5 MHz
VCC 4.5 V VCC < 4.5 V fs = 30 to 34 kHz
Typ. (Note 1)
Max
Unit
Power Supply Voltage AVcc VCC AVss VSS
VCC
2.7
5.5
V
AD0 to 15
VIL
0.8 0.6
Input Low Voltage
P20 to 27, P32 to 37, P42, P50 to 57, P60 to 67, P70 to 73, P80 to 86, P93, P96, P97 to 37, PA0 to A7
RESET , NMI , P40 to
0.3 VIL1 0.3 VCC
VCC VIL2 VIL3 VIL4 VIH VCC
2.7 to 5.5 V 0.25 VCC 0.3 0.2 VCC 4.5 V 2.2 2.0 V
41, P87, P90 to 92, P94, P95
EA , AM8/ 16
X1 AD0 to 15
VCC < 4.5 V
Input High Voltage
P20 to 27, P32 to 37, P42, P50 to 57, P60 to 67, P70 to 73, P80 to 86, P93, P96, P97 to 37, PA0 to A7
RESET , NMI , P40 to 41, P87, P90 to 92, P94, P95 EA , AM8/ 16
VIH1
0.7 VCC VCC VCC 2.7 to 5.5 V 0.75 VCC VCC 0.3 0.3
VIH2 VIH3 VIH4
X1
0.8 VCC
Note: Typical values are for Ta
25C and Vcc
5 V unless other wise noted.
91PW11-16
2003-03-31
TMP91PW11
4.2
DC Characteristic (2/2) (Vss
Parameter Symbol
VOL
0 V, Ta
40 to 85C)
Min Typ. (Note 1) Max
0.45 7 10%) 16 10%) 2.4 4.2 1.0 3.5 0.02 0.2 2.0 50 80 0.4 1.0 V 80 150 150 300 45 30 18 3.5 55 40 30 10 20 11 7.5 1.8 200 52 52 40 10 0.2 20 50 A A mA mA k 0.05 5 10 6.0 150 200 10 mA V mA
Condition
I OL 1.6 mA (VCC 2.7 to 5.5 V) VOL 1.0 V (VCC 3 V VOL 1.0 V (VCC 5 V
Unit
V
Output Low Voltage (except PA0 to PA5)
Output Low Current (PA0 to 5)
IOLA
VOH1 Output High Voltage VOH2
I OH 400 A (VCC 3 V 10%) I OH 400 A (VCC 5 V 10%) V EXT 1.5 V R EXT 1.1 k (VCC 5 V 10% only) 0.0 0.2 VIL2 VIH 2 VCC VCC fc VIN VIN VCC VCC
Darlington Drive Current (8 Output Pins max.) Input Leakage Current Output Leakage Current Power Down Voltage (at STOP, RAM Back up)
RESET Pull Up Resistor
IDAR (Note 2) ILI ILO VSTOP
A V k pF
0.2 VCC, 0.8 VCC 5V 3V 10% 10%
RRST CIO VTH
Pin Capacitance Schmitt Width
RESET , NMI , P40, P41, P87,
1 MHz
P90 to 92, P94, P95 Programmable Pull Down Resistor Programmable Pull Up Resistor NORMAL RUN IDLE2 IDLE1 NORMAL RUN IDLE2 IDLE1 SLOW RUN IDLE2 IDLE1 Ta STOP Ta Ta 50C 70C 85C VCC 2.7 to 5.5 V VCC fs 3V 10% 32.768 kHz (Typ.: Vcc 3.0 V) VCC fc 3V 10% 12.5 MHz (Typ: VCC 3.0 V) RKL RKH ICC VCC VCC VCC VCC VCC fc 5V 3V 5V 3V 5V 10% 10% 10% 10% 10% 10 30 50 100
25 MHz
13 8 4.8 1.1 110 30 25 15
Note 1: Typical values are for Ta
25C and Vcc
5 V unlesss otherwise noted.
Note 2: I-DAR is guranteed for total of up to 8 ports.
91PW11-17
2003-03-31
TMP91PW11
4.3
AC Characteristics
(1) Vcc 5V 10% (fc (fs 4 to 20 MHz) 30 to 34 kHz) External-bus access isn't supported in over 20 MHz. Variable Min Max
50 2x 0.5x 1.5x 0.5x 0.5x x 0.5x 0.5x x 1.5x 0.5x 40 20 70 15 20 40 25 20 25 50 25 3.0x 3.5x 2.0x 2.0x 0 x 2.0x 2.0x 0.5x n mode) n mode) n mode) 2.0x 0 2.5x 2.5x 50 200 120 206 200 15 40 55 15 3.5x 3.0x 90 80 125 36 175 200 40 55 65 60 85 0 48 85 70 16 129 108 100 5 33.3 s
No. Symbol
1 tOSC 2 tCLK 3 tAK 4 tKA 5 tAL 6 tLA 7 tLL 8 tLC 9 tCL 10 tACL 11 tACH 12 tCA 13 tADL 14 tADH 15 tRD 16 tRR 17 tHR 18 tRAE 19 tWW 20 tDW 21 tWD 22 tAWH 23 tAWL 24 tCW 25 tAPH 26 tAPH2 27 tCP Osc. Period ( x) CLK width
Parameter
16 MHz 20 MHz Unit Min Max Min Max
62.5 85 11 24 16 11 23 6 11 38 44 6 133 154 65 60 0 35 60 45 10 85 70 50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
A0 to 23 Valid CLK Hold CLK Valid A0 to 23 Hold A0 to 15 Valid ALE fall ALE fall A0 to 15 Hold ALE High pulse width ALE fall
RD / WR fall
RD / WR rise ALE rise A0 to 15 Valid A0 to 23 Valid RD / WR fall RD / WR fall
RD / WR rise A0 to 23 Hold A0 to 15 Valid D0 to 15 input A0 to 23 Valid D0 to 15 input RD fall D0 to 15 input RD Low pulse width RD rise D0 to 15 Hold RD rise A0 to 15 output WR Low pulse width D0 to 15 Valid WR rise
WR rise D0 to 15 Hold A0 to 23 Valid A0 to 15 Valid RD / WR fall WAIT input (1WAIT WAIT input (1 WAIT WAIT Hold (1 WAIT
A0 to 23 Valid PORT input A0 to 23 Valid PORT Hold WR rise PORT Valid
AC Measuring Conditions Output Level: High 2.2 V /Low 0.8 V, CL
50 pF
(However CL 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , R/ W , CLK) Input Level: High 2.4 V / Low 0.45 V (AD0 to AD15) High 0.8 Vcc / Low 0.2 Vcc (Except for AD0 to AD15)
91PW11-18
2003-03-31
TMP91PW11
(2) Vcc 3V 10% (fc (fs 4 to 12.5 MHz) 30 to 34 kHz) Variable Min
80 2x 0.5x 1.5x 0.5x 0.5x x 0.5x 0.5x x 1.5x 0.5x 40 30 80 35 35 60 35 40 50 50 40 3.0x 3.5x 2.0x 2.0x 0 x 2.0x 2.0x 0.5x n mode) n mode) n mode) 2.0x 0 2.5x 2.5x 50 200 120 250 200 25 40 120 40 3.5x 3.0x 130 100 160 80 40 110 125 115 120 0 55 120 40 0 150 140
No. Symbol
1 tOSC 2 tCLK 3 tAK 4 tKA 5 tAL 6 tLA 7 tLL 8 tLC 9 tCL 10 tACL 11 tACH 12 tCA 13 tADL 14 tADH 15 tRD 16 tRR 17 tHR 18 tRAE 19 tWW 20 tDW 21 tWD 22 tAWH 23 tAWL 24 tCW 25 tAPH 26 tAPH2 27 tCP Osc. Period ( x) CLK width
Parameter
12.5 MHz Min
80 120 10 40 5 5 20 5 0 30 70 0 130 155 45
Max
33.3 s
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
A0 to 23 Valid CLK Hold CLK Valid A0 to 23 Hold A0 to 15 Valid ALE fall ALE fall A0 to 15 Hold ALE High width ALE fall RD / WR fall
RD / WR rise ALE rise A0 to 15 Valid A0 to 23 Valid RD / WR fall RD / WR fall
RD / WR rise A0 to 23 Hold A0 to 15 Valid D0 to 15 input A0 to 23 Valid D0 to 15 input RD fall D0 to 15 input RD Low pulse width RD rise D0 to 15 Hold RD rise A0 to 15 output WR Low pulse width D0 to 15 Valid WR rise
WR rise D0 to 15 Hold A0 to 23 Valid A0 to 15 Valid RD / WR fall WAIT input (1 WAIT WAIT input (1 WAIT WAIT Hold (1 WAIT
A0 to 23 Valid PORT input A0 to 23 Valid PORT Hold WR rise PORT Valid
AC Measuring Conditions Output Level: High 0.7 Vcc / Low 0.3 Vcc, CL Input Level: High 0.9 Vcc / Low 0.1 Vcc 50 pF
91PW11-19
2003-03-31
TMP91PW11
(1) Read Cycle
tOSC X1/XT1 tCLK CLK tAK A0 to 23 tKA
CS0 to 2
R/W
tAWH tAWL
tCW
WAIT tAPH tAPH2
Port Input
tADH RD tACH tACL tLC AD0 to 15 tAL ALE tLL A0 to 15 tLA tRR tRSH RD RAS ttADL
tCA tRAE tHR D0 to 15 tCL
91PW11-20
2003-03-31
TMP91PW11
(2) Write Cycle
X1/XT1
CLK
A0 to 23
CS0 to 2
R/W
WAIT
Port Output tCP WR, HWR tWW tDW AD0 to 15 A0 to 15 D0 to 15 tWD
ALE
91PW11-21
2003-03-31
TMP91PW11
4.4
AD Conversion Characteristics (Vss 0 V, AVcc Vcc, AVss Vss, Ta
40 to 85 C)
Vcc 5 V 10%, (fc 4 to 25 MHz) Vcc 3 V 10%, (fc 4 to 12.5 MHz)
Parameter
AD analog reference supply voltage ( ) AD analog reference supply voltage ( ) Analog reference voltage Analog reference voltage Analog input voltage Analog input impedance Analog reference voltage supply current 1 0
Symbol
VREFH VREFL AVCC AVSS VAIN RAIN IREF
TestConditions
Min
Vcc Vss Vcc Vss VREFL 0.2 0.2
Typ.
Max
Vcc Vss Vcc Vss 5 0.2 VREFH 0.2
Unit
V
k mA A LSB
Vcc Vcc Vcc
5V 3V
10% 10% 0.02
3.7 2.2 5.0 3 3
2.7 to 5.5 V
Total tolerance (excludes quantization error)
ET
Vcc 5 V 10% Vcc 3 V 10%
Note 1: 1LSB
(VREFH -VREFL)/210[V]
Note 2: Power supply current ICC from the VCC pin includes the power supply current from the AVCC pin.
4.5
Serial Channel Timing (Serial channel 2, 3 and 4)
(1) SCLK Input Mode Parameter Symbol
tSCY tOSS tOHS tHSR tSRD
Variable Min
16X tSCY/2 5X 0 tSCY 5X 100 5X 100 50
32.768 MHz (Note)
12.5 MHz Min
1.28 s 190 ns 300 ns 0
20 MHz Min
0.8 s 100 ns 150 ns 0
Max
Min
488 s 91.5 s 152 s 0
Max
Max
Max
SCLK cycle Output Data Rising edge of SCLK SCLK edge* Output Data hold SCLK edge* Input Data hold SCLK edge* effective data input
336 s
780 ns
450 ns
* It is rising edge in using rising edge mode and falling edge in using falling edge mode. (2) SCLK Output Mode Parameter
SCLK cycle (Programmable) Output Data SCLK rising edge SCLK rising edge Output Data hold SCLK rising edge Input Data hold SCLK rising edge effective data input
Symbol
tSCY tOSS tOHS tHSR tSRD tSCY
Variable Min
16X 2X 80 0 tSCY 2X 150 150
32.768 MHz (Note)
12.5 MHz Min
1.28 s 970 ns 80 ns 0
20 MHz Min
0.8 s 550 ns 20 ns 0
Max
8192X
Min
488 s 427 s 60 s 0
Max
250 ms
Max
655.36 s
Max
409.6 s
2X
428 s
970 ns
550 ns
91PW11-22
2003-03-31
TMP91PW11
(3) SCLK Input Mode (UART mode) Parameter
SCLK cycle Low level SCLK Pulse width High level SCLK Pulse width
Symbol
tSCY tSCYL tSCYH
Variable Min
4X 2X 2X 20 5 5
32.768 MHz (Note)
12.5 MHz Min
340 ns 165 ns 165 ns
20 MHz Min
220 ns 105 ns 105 ns
Max
Min
122 s 6s 6s
Max
Max
Max
Note: fs is used as system clock or input clock to prescaler.
91PW11-23
2003-03-31
TMP91PW11
Timing Chart for I/O Interface Mode
tSCY SCLK
tOSS Output Data TxD 0
tOHS 1 2 3
tSRD Input Data RxD Valid Valid
tHSR Valid Valid
Note:
SCLK is reversed in SCLK input falling mode.
91PW11-24
2003-03-31
TMP91PW11
4.6
Timer/Counter Input Clock (TI0, TI4, TI5, TI6, TI7)
Parameter Symbol
tVCK tVCKL
Variable Min
8X 4X 4X 100 40 40
12.5 MHz Min
740 360 360
20 MHz Min
500 240 240
Max
Max
Max
Unit
ns ns ns
Clock Cycle Low level pulse width High levelpulse width
tVCKH
4.7
Interrupt and Capture
(1) NMI , INT0 interrupts Parameter Symbol
tINTAL tINTAH
Variable Min
4X 4X
12.5 MHz Min
320 320
20 MHz Min
200 200
Max
Max
Max
Unit
ns ns
NMI , INT0 Low level pulse width NMI , INT0 High level pulse width
(2) INT4 to 7 Parameter
INT4 to INT7 Low level pulse width INT4 to INT7 High level pulse width
Symbol
tINTBL tINTBH
Variable Min
4X 4X 100 100
12.5 MHz Min
420 420
20 MHz Min
300 300
Max
Max
Max
Unit
ns ns
4.8
Serial Bus Interface Timing
(1) I2C bus Mode Parameter Symbol
tGSTA tHD: STA tLOW tHIGH tHD:IDAT tSU:IDAT tHD:ODAT tODAT tFSDA tFDRC tSU:STO
Variable Min
3X 2nX 2nX 2nX 8X 0 250 7X 2nX 3X 2nX 2nX 16X tHD:ODAT
Typ
Max
Unit
s s s s ns ns s s s s s
START command SDA fall Hold time START condition SCL Low level pulse width SCL High level pulse width Data hold time (input) Data set-up time (input) Data hold time (output) Data output SCL Rising edge STOP command SDA falling edge SDA Falling edge SCL Rising edge Set-up time STOP condition
11X
Note:
"n" value is set by SBICR1
Stop Command
Start Command
SDA
tGSTA tHD:ODAT tLOW tODAT tFSDA
tFDRC
SCL
tHIGH tHD:STA tHD:IDAT tSU:IDAT tSU:ST
91PW11-25
2003-03-31
TMP91PW11
(2) Clocked-synchronous 8-bit SIO Mode a. SCK Input Mode Parameter
SCK cycle SCK falling edge Output data Input data SCK rising edge Output data hold Input data hold SCK rising edge SCK rising edge
Symbol
tSCY2 tOHS2 tOSS2 tHSR2 tISS2
Variable Min
25X 6X tSCY2/2 6X 0 6X
Max
Unit
s s s ns ns
b. SCK Output Mode Parameter
SCK cycle SCK falling edge Output data Input data SCK rising edge Output data hold Input data hold SCK rising edge SCK rising edge
Symbol
tSCY2 tOHS2 tOSS2 tHSR2 tISS2
Variable Min
25X 2X tSCY2/2 2X 0 2X
Max
211X
Unit
s s s s ns
tSCY2
tOSS2 tISS2
SCK (Input/Output
tOHS2 SO (Output data) tHSR2 SI (Input data)
91PW11-26
2003-03-31
TMP91PW11
4.9
Timing Chart for Serial Channel 0,1
a. SCK input mode Parameter
SCK cycle SCK falling edge SCK rising edge SCK rising edge Output data hold Effective data input Input data hold
Symbol
tSCY tSKDO tSRD tHSR
Variable Min
16X 6X tSCY 6X 2X
Max
Unit
ns ns ns ns
b. SCK output mode Parameter
SCK cycle SCK falling edge SCK rising edge SCK rising edge Output data hold Effective data input Input data hold
Symbol
tSCY tSKDO tSRD tHSR
Variable Min
16X 2X tSCY 2X 2X
Max
Unit
ns ns ns ns
tSCY tSCL tSCH
SCK
tSKDO SO (Output data) tSRD tHSR SI (Input data) Valid Valid Valid Valid
91PW11-27
2003-03-31
TMP91PW11
4.10
SCOUT pin AC characteristics
Parameter Symbol
tSCH 5V 3V 5V 3V 10% 10% tSCL 10% 10% 0.5X 0.5X 10 20 30 20 15 0.5X 0.5X 10 20 30 20 15
Variable Min Max
12.5 MHz Min
20 MHz Max Min
Unit
ns ns ns ns
High-level pulse width VCC VCC Low-level pulse width VCC VCC
Measurement condition Output level: High 2.2 V / Low 0.8 V, CL 10 pF
tSCH tSCL
SCOUT
91PW11-28
2003-03-31
TMP91PW11
4.11
Timing Chart for Bus Request (BUSRQ ) / Bus Acknowledge ( BUSAK )
(Note 1)
CLK tBRC BUSRQ tCBAL tBRC tCBAH
BUSAK tBAA AD0 to AD15, A0 to A23, CS0 to CS2, R/W tABA (Note 2)
(Note 2) RD, WR, HWR
ALE
Parameter
Symbol
tBRC tCBAL tCBAH tABA tBAA
Variable Min
120 1.5X 0.5X 0 0
WAIT
12.5 MHz Min
120 120 40 0 0 240 80 80 80
20 MHz Min
120 195 65 0 0 80 80
BUSRQ
Max
Max
Max
Unit
ns ns ns ns ns
BUSRQ set-up time to CLK
CLK CLK
BUSAK falling edge BUSAK rising edge
Output Buffer is off to BUSAK
BUSAK
80 80
to Output Buffer is on.
Note 1: The Bus will be released after the during Wait cycle.
request is inactive, when the
is set to 0
Note 2: This line shows the output buffer is off-state. It doen't indicate the signal level is fixed. Just after the bus is released, the signal level which is set before the bus is released is kept dynamically by the external capacitance. Therefore, to fix the signal level by an external resistor during bus releasing, designing is executed carefully because the level - fix will be delayed. The internal programmable pull-up/pull-down resistor is switched active/non-active by an internal signal.
91PW11-29
2003-03-31
TMP91PW11
4.12
Read operation in PROM mode
DC/AC characteristics
Ta 25 5C Vcc 5V 10%
Parameter
VPP Read Voltage Input High Voltage (A0 to A16, CE , OE , PGM ) Input Low Voltage (A0 to A16, CE , OE , PGM ) Address to Output Delay
Symbol
VPP VIH1 VIL1 tACC
Condition
Min
4.5 2.2 0.3
Max
5.5 VCC 0.8 2.25TCYC 0.3
Unit
V V V ns
CL
50 pF
TCYC
400 ns (10 MHz Clock)
200 ns
4.13
Program operation in PROM mode
DC/AC characteristics
Ta 25 5C Vcc 6.25 V 0.25 V
Parameter
Programming Supply Voltage Input High Voltage (D0 to D7, A0 to A16, CE , OE , PGM ) Input Low Voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VCC Supply Current VPP Supply Current
PGM Program Pulse Width
Symbol
VPP VIH VIL ICC IPP tPW
Condition
Min
12.50 2.6 0.3
Typ
12.75
Max
13.00 VCC 0.8 50 50 0.3
Unit
V V V mA mA ms
fc VPP CL
10 MHz 13.00 V 50 pF 0.095 0.1
0.105
91PW11-30
2003-03-31
TMP91PW11
4.14
Timing chart of read operation in PROM mode
A0 to A16
CE
OE
PGM tACC
D0 to D7
Data output
91PW11-31
2003-03-31
TMP91PW11
4.15
Timing chart of program operation in PROM mode
High-Speed Programming formula
A0 to A16
CE
OE
D0 to D7
Unknown
Data-in stable
Data-out valid
tPW PGM
VPP
Note 1: The power supply of VPP (12.75 V) must be turned on at the same time or the later time for a power supply of VCC and must be clear power-on at the same time or early time for a power supply of VCC. Note 2: The pulling up/down device on condition of VPP 12.75 V suffers a damage for the device.
Note 3: The maximum spec of VPP pin is 14.0 V. Be carefull a overshoot at the programming.
91PW11-32
2003-03-31

▲Up To Search▲

Price & Availability of TMP91PW11F

	To Download TMP91PW11F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .